三個緩沖區,先進先出 first in – first out,第一個截圖最后說了,要是保證緩存的就是要發送的,請清除FLUSH_TX 但是實際沒用好像,待測試
If the TX FIFO (PRX) contains more than one payload to a PTX, payloads are handled using the first in –
first out principle. The TX FIFO (PRX) is blocked if all pending payloads are addressed to a PTX where the
link is lost. In this case, the MCU can flush the TX FIFO (PRX) by using the FLUSH_TX command.也就是修改下面這個函數
void NRF24L01_PacketAckData(u8*pBuf,u8 len)//發送數據包,用于發送模式2/4
{
NRF24L01_CE=0;
NRF24L01_Write_Buf(W_ACK_PAYLOAD,pBuf,len);
NRF24L01_CE=1;
}
void NRF24L01_PacketAckData(u8*pBuf,u8 len)//發送數據包,用于發送模式2/4
{
NRF24L01_CE=0;
NRF24L01_Write_Reg(FLUSH_TX, 0xff);
NRF24L01_Write_Buf(W_ACK_PAYLOAD,pBuf,len);
NRF24L01_CE=1;
}
不過也僅限于提前裝載ack數據的方案