標題: 編程和繪制原理圖完成數字電路設計 [打印本頁] 作者: heicad 時間: 2014-10-17 18:51 標題: 編程和繪制原理圖完成數字電路設計 1.針對開發板晶振頻率分頻1H在脈沖
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity pinlv1Hz is
Port(clk:in std_logic;
CP:OUT std_logic);
end;
Architecture dd of pinlv1Hz is
signal q:std_logic_vector(24 downto 0);
SIGNAL C:std_logic;
begin
process(clk)
begin
if clk'event and clk='1' then q<=q+1;
if q=9999999 then q<="0000000000000000000000000";C<=not C;
end if;
end if;
end process;
CP<=C;
end;
綜合無誤后點file--creat/Update/Creat Symbol files for current file生成元件符號
2.編輯60s計數器
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity court60 is
Port(clk:in std_logic;
q:out std_logic_vector(6 downto 0));
end;
Architecture dd of court60 is
signal qq:std_logic_vector(6 downto 0);
begin
process(clk)
begin
if clk'event and clk='1' then qq<=qq+1;
if qq=59 then qq<="0000000";
end if;
end if;
end process;
q<=qq;
end;
綜合無誤后點file--creat/Update/Creat Symbol files for current file生成元件符號
3。創造一個除法器宏模塊
創造一個除法器宏模塊完成60進制分各位十進制，是為6進制
4。編輯一個6位寬和四位寬總線變兩個4單根線的程序輸出程序
Library ieee;
Use ieee.std_logic_1164.all;
entity zx64 is
Port(q:in std_logic_vector(6 downto 0);
qq:in std_logic_vector(3 downto 0);
x0,x1,x2,x3:buffer std_logic;
y0,y1,y2,y3:out std_logic);
end;
Architecture dd of zx64 is
begin
y0<=q(0);
y1<=q(1);
y2<=q(2);
y3<=q(3);
x0<=qq(0);
x1<=qq(1);
x2<=qq(2);
x3<=qq(3);
end;
綜合無誤后點file--creat/Update/Creat Symbol files for current file生成元件符號
5.便兩位分時現實程序
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity fenshi is
Port(clk,a0,a1,a2,a3,b0,b1,b2,b3:in std_logic;
y0,y1,y2,y3,w0,w1:out std_logic);
end;
Architecture dd of fenshi is
signal q:std_logic_vector(7 downto 0);
begin
process(clk,a0,a1,a2,a3,b0,b1,b2,b3)
begin
if clk'event and clk='1' then q<=q+1;
if q<128 then
y0<=a0;y1<=a1;y2<=a2;y3<=a3;w0<='0';w1<='1';
else
y0<=b0;y1<=b1;y2<=b2;y3<=b3;w0<='1';w1<='0';
end if;
end if;
end process;
end;
綜合無誤后點file--creat/Update/Creat Symbol files for current file生成元件符號
6。編寫一個7段顯示碼程序顯示二進制位10進制
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity diaplay is
Port(q0,q1,q2,q3:in std_logic;
y6,y5,y4,y3,y2,y1,y0:out std_logic);
end;
Architecture dzb of diaplay is
signal qq:std_logic_vector(3 downto 0);
signal Q: std_logic_vector(6 downto 0);
begin
qq<=q3&q2&q1&q0;
----------------------------
process(qq)
begin
case qq is
when "0000"=>Q<="0000001"; --段碼顯示開發板共陽極，所以0顯示，1不顯示。
when "0001"=>Q<="1001111" ;
when "0010"=>Q<="0010010" ;
when "0011"=>Q<="0000110" ;
when "0100"=>Q<="1001100" ;
when "0101"=>Q<="0100100" ;
when "0110"=>Q<="0100000" ;
when "0111"=>Q<="0001111" ;
when "1000"=>Q<="0000000" ;
when "1001"=>Q<="0000100" ;
when others=>null;
end case;
end process;
y6<=q(6);y5<=q(5);y4<=q(4);y3<=q(3);y2<=q(2);y1<=q(1);y0<=q(0);
end;
綜合無誤后點file--creat/Update/Creat Symbol files for current file生成元件符號。
注意：以上編寫如果用兩位直接組合成四位二進制計數器，則無需用除法器。其他模塊也根據個人習慣可以不同。
7.建立原理圖文件
畫圖鏈接電路，在綜合無誤后，與開發板管腳對應相連，再綜合無誤后即可仿真。
注意：硬件仿真時，對于不用的管腳要設置成三態輸出。
