fpga常用功能代碼分享

ID:253883 · 發(fā)表于 2017-12-3 10:45

eda的代碼
一、多路選擇器
1二選一

modulemux21 (a,b,s,y);

            input a,b,s;
                  output y;


                     assign y = s ? a : b;
endmodule

2四選一

modulemux41(a,b,c,d,sel,y);

               input a,b,c,d;
                  input [1:0]sel;
                  output y;
                  reg y;
                  always@(*)
                        begin
                     case (sel)
                     2'b00:y<=a;
                           2'b01:y<=b;
                           2'b10:y<=c;
                           2'b11:y<=d;
                           default:y<=a;
                           endcase
                           end
                  Endmodule
四選一測試代碼
`timescale 1ns/1ns
`define period_clk 20
module mux41_tb;

reg a,b,c,d;
reg[1:0] sel;
wire  y;

mux41 mux41_0(
   .a(a),
               .b(b),
               .c(c),
               .d(d),
               .sel(sel),
               .y(y)

);

initial begin
a=0;
      b=0;
      c=0;
      d=0;
      sel=0;
      #(`period_clk*100)
      $stoop;
      end
      always #(`period_clk)  a=~a;
      always #(`period_clk*5)  b=~a;
      always #(`period_clk*10)  c=~a;
always #(`period_clk*15)  d=~a;
      always #(`period_clk*30)  sel=sel +1;

      endmodule

二、D觸發(fā)器
module DFF1(CLK,D,Q);

output Q ;

input CLK,D ;

reg Q ;

always@(posedge CLK)

Q <=D;

endmodule

電平觸發(fā)型鎖存器
moduleLATCH1 (CLK,D,Q);
output Q;
input CLK,D;
reg Q;
always@ (D or CLK)
if(CLK) Q<=D;
endmodule

含異步復(fù)位/時(shí)鐘使能型觸發(fā)器

module DFF2(CLK,D,Q,RST,EN);

output Q;

input CLK,D,RST,EN;

reg Q;

always@(posedge CLK or negedge RST)

begin

if (!RST) Q<=0;

else if (EN) Q<=D;

end

endmodule

完整的Word格式文檔51黑下載地址（共27頁）：

fpga代碼(1).doc (210 KB, 下載次數(shù): 21)