基于verilog語(yǔ)言的交通信號(hào)燈設(shè)計(jì)分享

ID:377043 · 發(fā)表于 2018-7-22 08:00

一、對(duì)一個(gè)南北向和東西向十字路口車輛信號(hào)燈和人行道信號(hào)燈的顯示進(jìn)行控制，車輛信號(hào)燈為紅黃綠三色，顯示順序?yàn)榫G黃紅循環(huán)顯示，人行道信號(hào)燈為紅綠兩色。南北向?yàn)橹鞲傻溃囕v信號(hào)燈顯示時(shí)間依次為綠燈90秒，黃燈5秒，紅燈40秒，交通燈點(diǎn)亮的同時(shí)2位LED燈倒計(jì)數(shù)顯示該等剩余秒數(shù)，當(dāng)車輛信號(hào)燈點(diǎn)亮綠燈時(shí)同時(shí)點(diǎn)亮人行道信號(hào)燈的綠燈，點(diǎn)亮?xí)r間為80秒，接著綠燈閃爍10秒，閃爍頻率1Hz，然后點(diǎn)亮紅燈45秒，如此依次進(jìn)行。東西向車輛信號(hào)燈顯示時(shí)間依次為綠燈35秒，黃燈5秒，紅燈95秒，交通燈點(diǎn)亮的同時(shí)2位LED燈倒計(jì)數(shù)顯示該等剩余秒數(shù)，當(dāng)車輛信號(hào)燈點(diǎn)亮綠燈時(shí)同時(shí)點(diǎn)亮人行道信號(hào)燈的綠燈，點(diǎn)亮?xí)r間為25秒，接著綠燈閃爍10秒，閃爍頻率1Hz，然后點(diǎn)亮紅燈100秒，如此依次進(jìn)行。

二、實(shí)驗(yàn)環(huán)境：

本次實(shí)驗(yàn)采用Cyclone IV EP4CE115F29芯片,系統(tǒng)時(shí)鐘為50MHz。實(shí)驗(yàn)環(huán)境為：1、PC機(jī)一臺(tái)。2、Altera的Quartus軟件一套。3、主芯片為Altera公司的DE2-115的EDA開發(fā)板一套。

verilog源碼：

module traffic_led(clkin,con11,con12,con21,con22,t11,t12,t21,t22);
input clkin;
output con11,con12,con21,con22,t11,t12,t21,t22;
reg [1:0] con11,con12,con21,con22;
reg [3:0] t11,t12,t21,t22;
reg [7:0] tcont,tout1,tout2; //剩余時(shí)間： t11:高位南北，t12：低位南北，t21：高位東西，t22：低位東西// //con11：南北車道，con12：南北人行，con21：東西車道，con22：東西人行//
always@(posedge clkin)
begin
tcont<=tcont+1;
if(tcont<=80)
begin
con11<=0;
con12<=0;
con21<=2;
con22<=2;
t11<=tout1/10;
t12<=tout1-(tout1/10)*10;
t21<=tout2/10;
t22<=tout2-(tout2/10)*10;
end
else if(tcont<=90)
begin
con11<=0;
con12<=1;
con21<=2;
con22<=2;
t11<=tout1/10;
t12<=tout1-(tout1/10)*10;
t21<=tout2/10;
t22<=tout2-(tout2/10)*10;
end
else if(tcont<=95)
begin
con11<=1;
con12<=2;
con21<=2;
con22<=2;
t11<=tout1/10;
t12<=tout1-(tout1/10)*10;
t21<=tout2/10;
t22<=tout2-(tout2/10)*10;
end
else if(tcont<=120)
begin
con11<=2;
con12<=2;
con21<=0;
con22<=0;
t11<=tout1/10;
t12<=tout1-(tout1/10)*10;
t21<=tout2/10;
t22<=tout2-(tout2/10)*10;
end
else if(tcont<=130)
begin
con11<=2;
con12<=2;
con21<=0;
con22<=1;
t11<=tout1/10;
t12<=tout1-(tout1/10)*10;
t21<=tout2/10;
t22<=tout2-(tout2/10)*10;
end
else if(tcont<=135)
begin
con11<=2;
con12<=2;
con21<=1;
con22<=2;
t11<=tout1/10;
t12<=tout1-(tout1/10)*10;
t21<=tout2/10;
t22<=tout2-(tout2/10)*10;
end
else
tcont<=0;
end
always@(posedge clkin)
begin
if(tcont<=90)
begin
tout1<=90-tcont;
tout2<=95-tcont;
end
else if(tcont<=95)
begin
tout1<=95-tcont;
tout2<=95-tcont;
end
else if(tcont<=130)
begin
tout1<=135-tcont;
tout2<=130-tcont;
end
else if(tcont<=135)
begin
tout1<=135-tcont;
tout2<=135-tcont;
end
end
endmodule