module zhuangtai(clk,rst,led0,led1,led2,led3);
input clk,rst;
output led0,led1,led2,led3;
wire [5:0]cnt;
wire clk_1hz;
fen1hz my_fen1hz(
.clk(clk),
.rst(rst),
.c_out(clk_1hz)
);
jishu my_jishu(
.clk(clk),
.rst(rst),
.c_out(cnt)
);
reg [1:0]curr_st;
reg [1:0]next_st;
parameter [1:0] IDLE=2'b00,
s1=2'b01,
s2=2'b10,
s3=2'b11;
always@(posedge clk or negedge rst)
if(!rst) curr_st<=IDLE;
else curr_st<=next_st;
always@(posedge clk or negedge rst)
begin
case(curr_st)
IDLE:begin
if(cnt==6'd15) next_st=s1;
else next_st=IDLE;
end
s1:begin
if(cnt==6'd25) next_st=s2;
else next_st=s1;
end
s2:begin
if(cnt==6'd29) next_st=s3;
else next_st=s2;
end
s3:begin
if(cnt==6'd36) next_st=IDLE;
else next_st=s3;
end
endcase
end
assign led0=(curr_st==IDLE)?0:1;
assign led1=(curr_st==s1)?0:1;
assign led2=(curr_st==s2)?clk_1hz:1;
assign led3=(curr_st==s3)?0:1;
endmodule
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