|
|
自己做的FPGA流水燈設(shè)計(jì)
vhdl源程序如下:
- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned .all;
- entity liushuideng is
- port(clk:in std_logic;
- led:out std_logic_vector(7 downto 0));
- end entity;
- architecture bhv of liushuideng is
- signal clk1:std_logic;
- begin
- process(clk)
- variable num:integer range 1 to 25000000;
- begin
- if rising_edge (clk)then
- if num=25000000 then num:=1;clk1<=not clk1;
- else num:=num+1;
- end if;
- end if;
- end process;
- process(clk1)
- variable n:integer range 0 to 3;
- begin
- if rising_edge (clk1) then
- if n=3 then n:=0;
- else n:=n+1;
- end if ;
- end if;
- case n is
- when 0=>led<="10001000";
- when 1=>led<="01000100";
- when 2=>led<="00100010";
- when 3=>led<="00010001";
- when others=>led<="00000000";
- end case;
- end process;
- end bhv;
所有資料51hei提供下載:
liushuideng.zip
(7.42 MB, 下載次數(shù): 40)
2019-7-3 11:41 上傳
點(diǎn)擊文件名下載附件
|
|
